This invention relates generally to demodulation systems and particularly to a demodulation system incorporating an FPLL (frequency and phase locked loop) for demodulating a digital signal.
FPLL demodulation circuits have been in common usage for a number of years and are fully described in U.S. Pat. Nos. 4,072,909 and 4,091,410, both of which are assigned to the assignee of this application and both of which are incorporated by reference herein. FPLLs are biphase stable and as such generally require some mechanism for assuring the proper polarity of demodulated output signal when, for example, they are used in television receiver circuits and the like. In the prior art circuits, an information signal (e.g. a data signal) was developed from the output of the limiter, which included a known component that indicated the lockup phase or polarity of the FPLL. This component was used to control an inverter for selectively inverting the FPLL output signal to assure a particular polarity.
The transmitted digital signal used with the invention includes a small in-phase pilot for enabling acquisition of the signal in the receiver. The pilot is provided in the data signal prior to modulation in the form of a DC offset voltage, and when demodulated in the receiver produces a corresponding DC voltage. The invention utilizes this DC voltage to determine the lockup polarity of the FPLL in the receiver and to correct the demodulated output signal polarity, if required.